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Revision as of 09:25, 9 December 2009 by (talk) (Added and corrected some more details.)
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The clock rate is 250 kHz so each symbol bit on the wire is 4 microseconds long (period time).

Frame rate is ?? Packet rate is typically around 44 Hz when all frames are sent.

RDM protocol additions

The name of the standard is: ANSI/ESTA 1.20, Entertainment Technology - Remote Device Management over USITT DMX512 ??? Mark (beginning of frames) Mark After Break (beginning of frames)

Mark time between packet Mark time between frames

DMX Timing table

Symbol length is 4 +/- 0.08us for 245 - 255 k baud/s, with non-return-zero between symbol bits. To transmit 8 data bits it take 11 symbols because the use of one start bit and two stop bits around each data byte. Slot/address number is known by counting slots from the long packet break in the beginning of each packet.

The maximum packet rate is 44 updates/s if all 513 slots are transmitted (start code + 512 values), but can be higher if fewer slots are transmitted. If only packets only consists of a start code + 24 values, up to 830 updates/s can be made.

Name Tx requirement Typical/suggested Tx Rx requirement
Break (a space)
(the packet start)
>= 92 us 100-120 us (Ujjal)
176 us (DMX512-A-2004)
>= 88 us
Mark after break
(in packet start)
>= 8 us 12 us (Ujjal) 4 us – < 1 s backward compatible
8 us – < 1 s DMX512-A-2004
Slot/frame width 44 us 44 us 44 us
Inter-slot/frame time
Mark time between slots
< 1 s minimal < 1 s
Mark before break
(Idle time after packet)
< 1 s minimal < 1 s
Break to Break time
(DMX2512 packet length)
1204 us – 1 s minimal 1196 us – 1.25 s

The Rx req. column shows what a receiver must be able to handle of valid timings.

Note that the minimum length of "Mark after break" was doubled from 4 to 8 us in 1990, and receivers can be backward compatible by accepting the shortest time.

The slot time must be precise, or else the receiver should discard the whole packet, e.g. if the second stop bit is missing.

There must be at least one packet with start code=0 per second, and a receiving product must specify what happens when this time is exceeded.

Here is a nice overview of the different parts of a DMX packet with timings etc.: These timing values matches the ones in the DMX standard from 2004.

Idle must be high level (mark level, "Mark before break".

As a receiver must handle varying "mark time between slots", it needs to synchronize to each start bit in each slot.

Use of category 5 UTP or STP

New cable types is used, and may be officially accepted.

(old link is

The cabling for DMX512-A should be described in the document called "BSR E1.27-1 -- Portable Control Cables for Use with USITT DMX512/1990 and E1.11 [DMX512-A]"

A PDF shows the research and measurements that shows cat. 5 cable is good enough for DMX.

The use of modular plugs like 8-position modular connector (8P8C or RJ45) or 6P4C (RJ11)?

The 8-position modular connector is allowed in the DMX512-A as an alternate connector if there is not space enough for XLR5 or for fixed installations in "controlled access areas". Pin-out:

Pin Function
1 data 1+
2 data 1-
3 data 2+
6 data 2-
4 Not assigned
5 Not assigned
7 Data link common for data 1
8 Data link common for data 1

Both common wires are mandatory, and must have same potential in equipment sockets.

Sender/receiver topologies

To avoid ground loops and improve reception performance, transmitters and/or receivers can be grounded/floating/non-isolated ??? There are different topologies, and not all will work together. There are no requirement for what topology to use in the DMX specification from 1990, so it was added to DMX512-A.

Transmitters should use "earth ground" as a reference for the positive/negative voltages that is put on the two data lines. If they don't, it must be clearly marked on the product and in the manual. Receivers should be ...?

More suggestions and info

Here is also a nice overview of the different parts of a DMX packet with timings etc.:


The power dissipation in the 120 Ohm terminating resistors depends on the differential voltage between the two data wires. If the transmitter only makes a 5 V differential voltage, the power dissipation is P= U*U/R= 5*5/120 = 208 mW.

According to the maximum absolute differential voltage allowed by the EIA485 standard is 6 V. This give the maximum power dissipation is P= U*U/R= 6*6/120 = 300 mW. So it is best to use 1/2 W resistors.

At there is an example wit D1+ at +5V and D1- at -5V, and considering page 12 in this document from TI it is presumably a wrong interpretation.

This web page cites RS485 as having a upper limit of +12/-7 V with respect to ground. This probably refers to common mode loading voltages that receivers must work with. I.e. one of the data wires is allowed to reach +12 or -7 V but the opposite wire must not be at the other extreme, but only differ by 6 V maximum.

Transceiver chips made for 5 V: Linear Technology LTC485:,C1,C1007,C1017,P2064 National semiconductor LMS485: National semiconductor DS75176B (used in Martin PAL 1200, Lite-Puter DX-625 and a cheap Eurolite DMX console)

a but the spec says that the differential maximum from transmitters is 6 V, according to

Debugging tips

Links to simple testers?

How can reverse polarity be detected?

  • The break at the very beginning of a packet must be low
  • If all transmitted data bytes have value zero, the DMX line should be low about 80 % of the time if there are no extra idle time between slots/frames or packets.