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This information is not complete. The purpose is to introduce the protocol and the details of a packet and maybe explain the required timing of the signal. --Beier 06:21, 28 January 2007 (PST)

The last version of the standard is called USITT DMX512-A and it is maintained by ESTA since 1998. In 2004 it was made an ANSI standard too, named "E1.11, USITT DMX512-A" or "ANSI E1.11-2004". In 2008 it was revised [1] .

DMX is characterized by its simplicity in how data are transferred from a controller to receiving equipment.


DMX is based on the balanced serial connection standard EIA-485-A (a.k.a RS485). Only 5-pin XLR meets the standard (and products may meet the requirement by supplying adapters). Since the revision in 1998 the cables itself are not specified in DMX512-A (so it can be specified in separate standards?) In general the cable must fulfill the EIA-485 requirements of 120 Ohms (around 250 kHz) shielded twisted pair. One transmitter must be connected to maximum 32 receivers.

  • Termination resistor tolerance is 120 Ohm +5 % / -10 % (108 – 126 Ohm).
  • Each receiver must not load the differential line with more than 125 pF.

Use of category 5 UTP or STP

Other cable types have been examined to determine how well they are for DMX usage (as loose cables or in fixed building installations). The last report more or less concludes that for fixed installations, unshielded twisted pair in CAT 5 is good enough, even when it is mixed with 120 Ohm cable meant for EIA-485. The pulses from reflections and general degradation is not significant and harmless. See the three parts at .

See also this point in USITT's DMX faq:

(old link is [2])

The cabling for DMX512-A should be described in the document called "BSR E1.27-1 -- Portable Control Cables for Use with USITT DMX512/1990 and E1.11 [DMX512-A]"

The 8-position modular connector is allowed in the DMX512-A as an alternate connector if there is not space enough for XLR5 or for fixed installations in "controlled access areas". Pin-out:

Pin Function
1 data 1+
2 data 1-
3 data 2+
6 data 2-
4 Not assigned
5 Not assigned
7 Data link common for data 1
8 Data link common for data 1

Both common wires are mandatory, and must have same potential in equipment sockets.

Transmitter/receiver topologies

To avoid ground loops between equipment and improve reception performance, the transmitters and receivers for the DMX line must use a good combination of transmitter/receiver topologies. Some are not allowed, some are accepted with warning labels and some are preferred. See .

Transmitters should use "earth ground" as a reference for the positive/negative voltages that is put on the two data lines. Receivers should be "isolated".

The protocol

A Universe contains 512 addresses and a single DMX line (cable) can only transmit one universe. I.e. a controller with two universes need two DMX lines (daisy chains including splitters). A universe is normally thought of as an address space (in the controller), the cables that transmits it and the equipment that receives it.

  • The DMX signal is made up of a sequence - called a packet - which is sent over and over again (to increase robustness).
  • It is up to the controller/transmitter to decide how many of the 512 values is sent. A shorter packet means faster cycles.
  • A receiver must be set or programmed to an address it listens to. If a receiver listens to multiple addresses, the set one is the first. (It depends on implementation.)
  • Multiple receiver can listen to the same address - the DMX system does not care.

A packet has the following sequence:

  • Break
  • Mark After Break (MAB)
  • The "start code" frame (Sometimes called address 0) Alternate start codes
  • 1-512 slots/frames with the values of the channels. The first value is for address "1", the next for address 2 etc.

(Note: A packet must have a minimum length in time)

  • A slot/frame contains the value for one address, has one start bit and two stop bits.
  • The address number is not sent over the lines, so the receiver must count the received slots from the start of the sequence to find the wanted value.
  • The start code is used to alter the meaning of the data bytes in the rest of the packet. The default is 0, and the remaining 255 values is rarely used (by definition 0 means dimmers, but is used for intelligent light as well).

Note that some people and texts use the words frame and packet in the opposite sense than stated here.


The clock rate is 250 kHz so each symbol bit on the wire is 4 microseconds long (period time).

Symbol length is 4 +/- 0.08us for 245 - 255 k baud/s, with non-return-zero between symbol bits. To transmit 8 data bits it take 11 symbols because the use of one start bit and two stop bits around each data byte. Slot/address number is known by counting slots from the long packet break in the beginning of each packet.

The maximum packet rate is 44 updates/s if all 513 slots are transmitted (start code + 512 values), but can be higher if fewer slots are transmitted. If only packets only consists of a start code + 24 values, up to 830 updates/s can be made.

Name Tx requirement Typical/suggested Tx Rx requirement
Break (a space)
(the packet start)
>= 92 us 100-120 us (Ujjal)
176 us (DMX512-A-2004)
>= 88 us
Mark after break
(in packet start)
>= 8 us 12 us (Ujjal) 4 us – < 1 s backward compatible
8 us – < 1 s DMX512-A-2004
Slot/frame width 44 us 44 us 44 us
Inter-slot/frame time
Mark time between slots
< 1 s minimal < 1 s
Mark before break
(Idle time after packet)
< 1 s minimal < 1 s
Break to Break time
(DMX2512 packet length)
1204 us – 1 s minimal 1196 us – 1.25 s

The Rx req. column shows what a receiver must be able to handle of valid timings.

Note that the minimum length of "Mark after break" was doubled from 4 to 8 us in 1990, and receivers can be backward compatible by accepting the shortest time.

The slot time must be precise, or else the receiver should discard the whole packet, e.g. if the second stop bit is missing.

There must be at least one packet with start code=0 per second, and a receiving product must specify what happens when this time is exceeded.

Here is a nice overview of the different parts of a DMX packet with timings etc.: These timing values matches the ones in the DMX standard from 2004.

Idle must be high level (mark level, "Mark before break".

As a receiver must handle varying "mark time between slots", it needs to synchronize to each start bit in each slot.

Sources and additional reading

Ujjal's DMX512 Pages (down-to-earth walk-through, also a good historical overview from before DMX )
ePanorama (thorough descriptions of most details, lots of links)
The anatomy of DMX512 (a nice, short overview)
DMX timings by Erwin Rol

History from mechanical dimming over analog lines, multiplexing, DMX and to ACN in three pages.

An other DMX signal/cable description

Thorough DMX description and a long list of good references to other sites and projects. Much better than a google search!

See also: