Difference between revisions of "Talk:DMX512-A"

Revision as of 16:43, 11 July 2009

Timings

The clock rate is 250 kHz so each symbol bit on the wire is 4 microseconds long (period time).

Frame rate is ?? Packet rate is typically around 44 Hz when all frames are sent.

RDM protocol additions

The name of the standard is: ANSI/ESTA 1.20, Entertainment Technology - Remote Device Management over USITT DMX512 ??? Mark (beginning of frames) Mark After Break (beginning of frames)

Mark time between packet Mark time between frames

DMX Timing table

Symbol length is 4 +/- 0.08us for 245 - 255 k baud/s, with non-return-zero between symbol bits. To transmit 8 data bits it take 11 symbols because the use of one start bit and two stop bits around each data byte.

Idle must be high level Note that "Mark after break" was changed from 4 to 8 us minimum length in 1990, and receivers can be backward compatible. The slot time must be precise, or else the receiver should discard the whole packet, e.g. if the second stop bit is missing.

There must be at least one packet with start code=0 per second, and a receiving product must specify what happens when this time is exceeded.

Ervin Rol has shown the timing values from the DMX standard.

Use of category 5 UTP or STP

New cable types is used, and may be officially accepted. http://www.usitt.org/standards/DMX512_FAQ.html#FAQ_08

The use of modular plugs like 8P8C (RJ45) or 6P4C (RJ11)

The cabling for DMX512-A should be described in the document called "BSR E1.27-1 -- Portable Control Cables for Use with USITT DMX512/1990 and E1.11 [DMX512-A]"

Sender/receiver topologiess

To avoid ground loops and improve reception performance, transmitters and/or receivers can be grounded/floating/non-isolated ??? http://www.usitt.org/standards/DMX512_FAQ.html#FAQ_15 There are different topologies, and not all will work together. There are no requirement for what topology to use in the DMX specification from 1990, so it was added to DMX512-A.

Transmitters should use "earth ground" as a reference for the positive/negative voltages that is put on the two data lines. If they don't, it must be clearly marked on the product and in the manual. Receivers should be ...?

More suggestions and info

Here is also a nice overview of the different parts of a DMX packet with timings etc.: http://www.erwinrol.com/index.php?stagecraft/dmx.php

Voltages

The power dissipation in the 120 Ohm terminating resistors depends on the differential voltage between the two data wires. If the transmitter only makes a 5 V differential voltage, the power dissipation is P= U*U/R= 5*5/120 = 208 mW.

According to http://focus.ti.com/lit/an/slla070c/slla070c.pdf the maximum absolute differential voltage allowed by the EIA485 standard is 6 V. This give the maximum power dissipation is P= U*U/R= 6*6/120 = 300 mW. So it is best to use 1/2 W resistors.

At http://www.dmx512-online.com/physl.html there is an example wit D1+ at +5V and D1- at -5V, and considering page 12 in this document from TI it is presumably a wrong interpretation.

This web page cites RS485 as having a upper limit of +12/-7 V with respect to ground. This probably refers to common mode loading voltages that receivers must work with. I.e. one of the data wires is allowed to reach +12 or -7 V but the opposite wire must not be at the other extreme, but only differ by 6 V maximum.

Transciever chips made for 5 V: Linear Technology LTC485: http://www.linear.com/pc/productDetail.jsp?navId=H0,C1,C1007,C1017,P2064 National semiconductor LMS485: http://www.national.com/mpf/LM/LMS485.html National semiconductor DS75176B (used in Martin PAL 1200, Lite-Puter DX-625 and a cheap Eurolite DMX console) http://www.national.com/mpf/DS/DS75176B.html

a but the spec says that the differential maximum from transmitters is 6 V, according to

Debugging tips

Links to simple testers?

How can reverse polarity be detected?

• The break at the very beginning of a packet must be low
• If all transmitted data bytes have value zero, the DMX line should be low about 80 % of the time if there are no extra idle time between slots/frames or packets.